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VLSI Design Engineer/Micro-architect responsible for designing cutting-edge communication systems from scratch using ASIC/FPGA with Verilog/SystemVerilog.
Physical Design Engineer at Apple implementing complex SoC designs on advanced (7nm and below) nodes: floorplanning, placement, clock tree synthesis, routing, ECOs, static timing and physical verification, low-power techniques, and CAD flow automation using Innovus/Fusion Compiler and TCL/Perl/Python scripting.
VLSI Design Engineer responsible for designing cutting-edge communication systems from scratch, including micro-architecture definition, RTL coding in Verilog/SystemVerilog, synthesis, timing analysis, and PPA optimization, collaborating closely with verification, DFT, and physical design teams.
About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
A hands-on IC role designing, integrating, and signing off RTL for blocks across an ultra-low-power RISC-V SoC — compute-fabric interconnect, memory interfaces, low-power/always-on logic, and peripherals — from microarchitecture spec through synthesis, timing closure, and tapeout. Core tech: SystemVerilog, CDC/LEC, SDC/STA, UPF low-power flows.
Senior engineer on JRC's semiconductor team designing radiation-hardened standard cell libraries for defense microelectronics: architecting and validating cells across advanced foundry nodes, characterizing PPA, simulating radiation-induced error rates, and supporting MPW test-chip runs. Core tools: Virtuoso, Spectre/HSPICE, DRC/LVS flows, plus C++/Python/TCL scripting.
Designs, writes, and tests C, C++, and Rust firmware for Geotab's GO telematics devices, developing features in areas like modem, GPS, vehicle data, and security. The role includes unit/integration testing, code reviews, debugging on embedded targets, and analyzing device health with SQL and Python on Google BigQuery.
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very…
Staff-level electrical engineer who architects, designs, and verifies flight-critical avionics hardware — mixed-signal circuit card assemblies and FPGA-based systems — for rocket engines and defense applications. Day to day spans RTL design, simulation, synthesis, timing closure (STA), board-level design, and hardware testing.
Designs and maintains the RTL-to-GDS physical design flow for AI accelerator chips using Cadence tools, scripting, and advanced 3nm+ process rules.
Senior engineer on Google's AI and Infrastructure team building and maintaining hardware emulation infrastructure for TPU ASIC projects. Day to day: compiling full-chip/multi-die SoC RTL on emulation platforms (Palladium/ZeBu/Veloce), bringing up high-speed interfaces, debugging, and driving pre-silicon bring-up and validation with design, verification, and software teams.
As System Validation engineer, you will play a crucial role in designing, testing, and troubleshooting Analog circuits within a laboratory setting. Your expertise in Analog electronics and proficiency in operating…
Senior engineer focused on digital design verification for IP and SoC designs using UVM and SystemVerilog. Responsibilities include developing verification environments, executing test scenarios, and collaborating with cross-functional teams to ensure hardware quality for automotive and industrial applications.
Salary: RM 12,000 – RM 18,000 per month About the role Design and own the business architecture for semiconductor manufacturing software solutions, covering MES, EAP, RTD, and related CIM applications. Translate fab…
Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off Define and drive IP‑level verification strategies, including test plans, coverage models,…
FPGA Design Engineer owning the design and implementation of FPGA-based interfaces (PCIe, I2C, SPI, high-speed GT) on Xilinx UltraScale+ and Versal platforms for quantum computing control systems.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Senior silicon design engineer on AMD's I/O IP team, developing Verilog RTL for host controller IP supporting next-gen high-speed I/O technologies (up to 40 Gb/s, e.g. USB4/Thunderbolt). Day-to-day involves designing reusable, functionally correct IP blocks, solving complex technical problems, and mentoring junior engineers.
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